A field programmable gate array (FPGA) is an array of uncommitted logic elements formed in an integrated circuit chip (IC) that can be interconnected to implement various circuit functions. An FPGA can generally be described as having one or more logic elements and a routing structure that routes signals to and from the logic elements.
The architecture of an FPGA refers to both the structure of the logic element(s) and the structure of the programmable routing resource. The logic elements vary greatly in type depending upon the purpose and function of the FPGA device. The logic elements can be as simple as multiple arrays of two-input NAND gates or as complex as multiplexers or lookup tables.
The routing structure interconnects the logic elements. The routing structure includes I/O blocks, routing wires, and programmable routing switches that selectively interconnect the wires. Routing switches can be configured in several different ways including anti-fuses, EPROM transistors, EEPROM transistors, pass transistors or pass gates controlled by SRAM cells, and tri-stateable multiplexer switches controlled by SRAM cells or EEPROM transistors.
The inventor was tasked with developing an FPGA suitable for space-bound technologies, such as satellites, interplanetary probes, or manned space shuttles. To date, there are no commercial FPGAs being used in space without shielding for long missions. Space application presents a whole host of design issues for semiconductor technologies. One problem concerns the varying degrees of radiation that an FPGA might encounter when traveling through the Van Allen belts encircling the earth. Radiation tends to vary from a few krads to hundreds of krads. The radiation factor affects choice of logic elements. Pass gates, for example, are not a good choice for the space environment because the NMOS transistor is susceptible to leakage and cross talk problems.
The inventor examined conventional FPGA architectures to determine whether they would be effective in space. FIGS. 1-4 show block representations of four generic classes of FPGA architectures. In all conventional architectures, the routing structure depends on the layout of the logic elements. The wires occupying the routing channels are generally straight segments (sometimes of varying lengths) that can be interconnected to form longer segments and connected to orthogonal wires to change direction.
FIG. 1 shows a symmetrical array architecture 20 having multiple logic elements 22 interconnected by vertical and horizontal wiring channels 24. In this architecture, the logic elements are separated from one another by the routing structure.
FIG. 2 shows a row-based architecture 30 having rows of logic elements 22 and primary wiring channels 24 running in parallel between the logic elements. There are additional wires (not shown) running transversely to the wiring channels 24 to connect to the logic elements.
FIG. 3 shows a conventional sea-of-gates architecture 40, in which the routing structure 24 overlays the logic elements 22.
FIG. 4 shows a hierarchical architecture 50 having local interconnects for connections to logic elements and global interconnects to route signals between blocks of logic elements.
The routing structure makes up the majority of the FPGA device. For example, conventional FPGAs consist of approximately 80% routing structure and 20% logic elements. Accordingly, only a small fraction of the FPGA is used to compute logic functions, while the majority of the FPGA is dedicated to routing signals to and from the logic elements. The proportionally larger routing structure enables broad adaptability and flexibility of the FPGA during programming.
However, to achieve greater logic functionality without increasing device size, it would be beneficial to increase the proportion of logic circuitry relative to routing structure on conventional FPGA devices.
Another drawback with conventional FPGA architectures is that routing delays between logic elements is dependent on many factors, including fanout (i.e., a wire net in which the output of one logic element drives multiple inputs of other logic elements), number of routing switches, and the location of the logic elements. To achieve high versatility, conventional FPGAs employ a large number of programmable routing switches. Signal paths from any two logic elements may be routed through various numbers of switches. As a result, path delays experienced by signals are typically different; that is, path delays differ for each logic element-to-logic element interconnect. The path delays cannot be determined until the designer has established where the logic elements are located and the final routing pattern used to interconnect the logic elements. Then, and only then, are the timing delays determinable.
It would be beneficial to devise an FPGA architecture in which path delays between any two logic elements is independent of location within the FPGA and fanout.
Although the inventor's quest began by contemplating use of FPGAs in space, the inventor has developed an FPGA routing architecture that broadly applies to all forms of FPGA devices, including special devices designed for space and commercial devices.